1. Field of the Invention
Embodiments of the invention relate to the field of nanotechnology, and more specifically, to nanotechnology in packaging.
2. Description of Related Art
Current first level interconnect technology involves metal, typically copper (Cu), bump formation on the silicon die and solder formation on the substrate side, using either stencil printing or electroplating. During chip attachment process, the solder reflows to form an electrical interconnect between the die and the substrate.
The existing interconnect technology has several problems or limitations. First, metals are susceptible to electro-migration, especially at high current densities. As the pitch and size of bumps become smaller for higher density interconnects, the current density carried by the metal bumps is also increasing. This leads to worsened electro-migration, posing serious reliability risks. Second, high density interconnects require decreased input/output (I/O) pitch and therefore bump size. Existing bump pitch for processor die is approximately 180 μm. It is extremely difficult to achieve nanometer-scale interconnect (e.g., in the order of 30 μm or less) using existing materials and processes partly because of the increased resistance and the electro-migration problem.